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STSR30
SYNCHRONOUS RECTIFIER SMART DRIVER FOR FLYBACK
s s
s s s
s
SUPPLY VOLTAGE RANGE: 4V TO 5.5V TYPICAL PEAK OUTPUT CURRENT: (SOURCE-SINK: 1.5A) OPERATING FREQUENCY: 20 TO 500 KHz INHIBIT BLANKING TIME: 700 ns AUTOMATIC TURN OFF FOR DUTY-CYCLE LESS THAN 14% POSSIBILITY TO OPERATE IN DISCONTINUOUS MODE
SO-8
DESCRIPTION STSR30 Smart Driver IC provides a high current outputs to properly drive secondary Power Mosfets used as Synchronous Rectifier in low output voltage, high efficiency Flyback Converters. From a synchronizing clock input, withdrawn on the secondary side of the isolation transformer, the IC generates a driving signal with set dead times with respect to the primary side PWM signal. The IC operation prevents secondary side shoot-through conditions at turn-on of the primary BLOCK DIAGRAM
switch providing anticipation in turn-off the output. This smart function is implemented by a fast cycle-after-cycle logic control mechanism, based on a high frequency oscillator synchronized by the clock signal. This anticipation is externally set through external component. A special Inhibit function, detecting the voltage across the Synchronous FET, allows to shut-off the drive output during discontinuous mode condition. A Disable pin allows turning off the device during no-load condition reducing overall current consumption.
January 2004
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STSR30
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol VCC OUTGATE DISABLE INHIBIT CK ESD PTOT TSTG TOP Parameter DC Input Voltage to SGLGND Max Gate Drive Output Voltage Max DISABLE Voltage Max INHIBIT Voltage (*) Clock Input Voltage Range (*) Human Body Model Continuous Power Dissipation at TA=105C SO-8 (No heatsink) Storage Temperature Range Operating Junction Temperature Range Value -0.3 to 6 -0.3 to VCC -0.3 to VCC -0.6 to VCC -0.3 to VCC 2 275 -40 to +150 -40 to +125 Unit V V V V V KV mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. (*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum
THERMAL DATA
Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient (*) SO-8 40 160 (*) Unit C/W C/W
(*) This value is referred to one layer pcb board with minimum copper connections for the leads. A minimum value of 120 C/W can be obtained improving thermal conductivity of the board
ORDERING CODES
TYPE STSR30 SO-8 STSR30D SO-8 (T&R) STSR30D-TR
CONNECTION DIAGRAM (top view)
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PIN DESCRIPTION
Pin N 1 Symbol INHIBIT Name and Function This input enables OUTGATE to work when its voltage is lower than the negative threshold voltage (VINHIBITVH the OUTGATE will be high for a minimum conduction time (tON(GATE)). In typical flyback converter application, it is possible to turn off the synchronous MOSFET when the current through it tends to reverse, allowing discontinuous conduction mode and providing protection to the converter from eventual sinking current from the load. A blanking time of 700ns allows operation when some voltage ringing is present during turn-off of primary switch. Absolute maximum voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10mA max. Gate Drive signal for Synchronous MOSFET. Anticipation [tANT] in turning off OUTGATE is provided when the clock input goes to low level. Reference for all the control logic signals. This pin is completely separated from the PWRGND to prevent eventual disturbances to affect the control logic. Reference for power signals, this pin carries the full peak currents for the output. The supply voltage range from 4.5V to 5.5V allows applications with logic gate threshold mosfets. UVLO feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage. This pin allows turning off the device completely when kept to low level. In this condition the IC power consumption is strongly reduced. When this pin goes to high value, OUTGATE turns to switching again according to the CK signal. The voltage on this pin sets the anticipation in turning off the OUTGATE. It is possible to choose among three different anticipation times by discrete partitioning of the supply voltage [ANT]. This input provides synchronization for IC's operations, being the transitions between the two output conditions based on a positive threshold, equal for the two slopes. A smart internal control logic mechanism using a 15MHz internal oscillator generates proper anticipation timing at the turn-off of each output. This feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual shoot-through situation on secondary side at both transitions. Clock revelation mechanism makes the operation of STSR30 particularly suitable for flyback adaptors application allowing correct operation during discontinuous mode. Absolute maximum positive voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10mA max.
2 3 4 5
OUTGATE SGLGND PWRGND VCC
6
DISABLE
7
SETANT
8
CK
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ELECTRICAL CHARACTERISTICS (VCC = 5V, CK = 100kHz, duty-cycle = 50%, VINHIBIT = -200mV, TJ = -40 to 125C, C1 = C2 = 100nF ceramic, unless otherwise specified.)
Symbol Parameter Test Conditions Min. Typ. 3.7 3.6 3.2 15 0.20 4.30 4.65 1.5 1.5 1.75 1 40 40 25 3.5 2.25 ns ns ns A Max. 4 4.5 50 0.45 Unit V mA A V SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT VCC Start Threshold Turn OFF Threshold After Start ICC Unloaded Supply Current OUTGATE = no load DISABLE = 0V GATE DRIVER OUTPUT OUTGATE Output Low Voltage Output High Voltage IOUT RDS(ON) tR tF tP Output Source Peak Current Output Sink Peak Current Output Series Source Resistance Output Series Sink Resistance Rise Time Fall Time IOUTGATE = -200mA IOUTGATE = 200mA TJ = 25C TJ = 25C
3.3
CLOAD = 5nF (Note 1) CLOAD = 5nF (Note 1)
Clock Propagation Delay to Turn ON No Load (Fig. 4) of OUTGATE VANT = 0 to 1/3VCC; no load VANT = 1/3VCC to 2/3VCC; no load VANT = 2/3VCC to VCC; no load -0.1 VDISABLE > VDP : ON VDISABLE < VDN : OFF 0.8 -0.1 TJ = 25C VINHIBIT = +200mV VINHIBIT = -200mV VINHIBIT = +200mV -30
TURN-OFF ANTICIPATION TIME tANT OUTGATE Turn-off Anticipation Time (Fig. 1)
150 225 300 0.1 1.7 1.5 0.2 0.1 -25 -100 1.5 700 1 0.8 14 19 1.2 2.4
ns
ISETANT
Leakage Current (Note 2)
A V V V A mV nA A ns V %
DISABLE VDP Positive Threshold Voltage VDN VHY II VH IH tBL Negative Threshold Voltage Hysteresis Voltage Input Current Threshold Voltage Leakage Current Blanking Time
INHIBIT (OUTGATE ENABLE)
SYNCHRONIZATION INPUT VCK Rise Threshold Voltage Fall Threshold Voltage DOFF Duty Cycle Shut Down Duty Cycle Turn ON after Shut Down
0.6 12
20
Note1: tR is measured between 10% and 90% of the final voltage; tF is measured between 90% and 10% on the initial voltage Note2: Parameter guaranteed by design
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Figure 1 : TIMING DIAGRAM
Figure 2 : STSR30 IN FLYBACK CONVERTER SECONDARY SIDE
Feedback Loop
TRANSFORMER
Vi
Cout MosfetN C1 100nF
Vo
PWM
2 4
+5V
5 C2 100nF 3 R1
PWRGND
OUTGate
+5V
SGLGND
R3
D3
Vcc
8
Ck
STSR30
DISABLE
SETANT
7
R2
1
INHIBIT
R5 D1
D2
+5V
Low = OFF High = ON
option
NOTES 1) Ceramic Capacitors C1 and C2 must be placed very close to the IC; 2) R1 and R2 set the anticipation time by partitioning the VCC voltage; 3) R3 is a pull-up resistor; 4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high; 5) D1 could be necessary to protect INHIBIT pin from negative voltages. 6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC 7) SGLGND layout trace must not include OUTGATE current paths.
6
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Figure 3 : STSR30 SYNCHRONIZATION TECHNIQUE
The synchronization is based on the revelation of the low level of the drain voltage of the synchronous rectifier. To avoid false triggering of the device during discontinuous mode, it is important that the lowest level of the ringing must be higher than the Ck threshold. Diode D3 and resistor R3 keep the Ck signal to high level even during the ringing. OUTGate is the complementary signal of the Ck with proper dead time setting to avoid cross-conduction.
Figure 4 : INHIBIT OPERATION OF OUTGATE IN DISCONTINUOUS CONDUCTION MODE
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Figure 5 : INHIBIT Threshold Voltage vs Temperature Figure 8 : RDS(ON) vs Temperature
Figure 6 : ICC vs CK Frequency
Figure 9 : Minimum TON(GATE)
Figure 7 : Rise and Fall Time vs Load Capacitor
Figure 10 : OUTGATE Turn-off Jitter with Minimum Anticipation Time
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SO-8 MECHANICAL DATA
DIM. A A1 A2 B C D E e H h L k ddd 0.1 5.80 0.25 0.40 mm. MIN. 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.04 0.043 0.013 0.007 0.189 0.150 0.050 0.244 0.020 0.050 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157
8 (max.)
0.04
0016023/C
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Tape & Reel SO-8 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.1 5.5 2.1 3.9 7.9 12.8 20.2 60 22.4 8.5 5.9 2.3 4.1 8.1 0.319 0.216 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.335 0.232 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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